1. Field of the Invention
The present invention relates to an active matrix type display device in which two adjacent pixels share one signal line, and a driving method of the display device.
2. Description of the Related Art
In recent years, an active matrix type display device using a thin-film transistor (TFT) as a switching element has been developed.
The display device includes a scanning line driving circuit (gate driver) which generates scanning signals in order to scan, in turn by row, a plurality of pixels arranged in a matrix form. The gate driver operates at an operation frequency lower than that of a signal line driving circuit (source driver) which supplies video signals to each of the pixels. Therefore, even if the gate driver is formed at the same time in the same process as that to form TFTs corresponding to each of the pixels, the gate driver can satisfy its specification.
Each pixel of the display device has a pixel electrode connected to a TFT, and a common electrode (common to all of the pixels) to which a common voltage Vcom is applied. In the active matrix type display device, to prevent deterioration of liquid crystals caused by sustained application of an electric field in one direction, inversion driving to invert polarities of a video signal Vsig from the source driver against the common voltage Vcom for each frame, line or dot has been performed generally.
Meanwhile, in mounting the display device, the gate driver and the source driver are disposed around a display panel (display screen), which has a large number of pixels disposed thereon. Wiring lines to electrically connect scanning lines (gate lines), and signal lines (source lines) on the display screen to the gate driver and the source driver are routed around the outside the display screen. At this time, it is strongly desired to make a routing area of the wiring lines smaller, that is, to achieve a reduction in area other than the display panel (i.e., to narrow the picture frame) from a point of view of miniaturizing information equipment having an active matrix display device built-in.
Therefore, in particular, a configuration of pixel wiring lines with half the number of source lines has been developed because the area occupied by the source lines can be made smaller, in order to narrow the picture frames of the display panel in the vertical direction (e.g., as shown in FIG. 5 of Jpn. Pat. Appln. KOKAI Publication No. 2004-185006).
FIG. 10 is a schematic view of an example of pixel wiring lines on a display screen to achieve such a narrowed picture frame. This example shares one source line with two adjacent pixels 100. In this case, TFTs 102 of the two adjacent pixels 100 (in the same row) are connected to respective different gate lines. In FIG. 10, for example, the TFT 102 of the pixel 100 in red (R) at the upper left is connected to a gate line G1 and a source line S1, and the TFT 102 of the neighboring pixel 100 in green (G) to the right is connected to a gate line G2 and the source line S1.
FIG. 11 illustrates the order of writing video signals Vsigs to each pixel 100 using the pixel wiring arrangement shown in FIG. 10. As illustrated in FIG. 11, the writing of the video signals Vsigs to each pixel 100 is executed in the order of the gate lines.
In the structure of the pixel wiring lines described above in which the number of the source lines is reduced by half, some adjacent columns of pixels have a source line therebetween, and other adjacent columns of pixels do not have a source line therebetween. As illustrated in the equivalent circuit of FIG. 12, at the points without source lines between pixels, there is parasitic capacitance between the pixels that is larger than at points where a source line is provided between adjacent pixels Among pixels having inter-pixel parasitic capacitance 104, voltage leakages occur, and as a result the electrical potential at the pixel 100 written first varies under the influence of the voltage at the pixel 100 written later. The variation in voltage appears as display unevenness on the screen. Since order of writing is fixed as depicted in FIG. 11, the display unevenness caused by the leakage always occurs at the same point.
FIG. 13 is a view illustrating an example of the display unevenness. FIG. 13 illustrates the display unevenness only of the pixels 100 of G so as to make the example clearly understandable. Here, the scanning order of the gate lines is expressed as G1, G2, G3, . . . , G8. At the pixels 100 of other colors which are depicted in a ground color black in FIG. 13, the electrical potential of the pixels 100 written first varies in a similar manner (described in detail later).
FIG. 14 shows configurations of each pixel when the display panel is a TFT liquid crystal display (LCD). Each pixel 100 is configured such that a liquid crystal (not shown) is held between the common electrode to which the common voltage Vcom is to be applied (not shown) and the pixel electrode connected to a source line through a TFT 102 which is also connected with a gate line. Holding electric charge at a liquid crystal capacitor Clc over a field period (frame period in the case of a non-interlace system) achieves the corresponding display. As a countermeasure against current leakage through the capacitor Clc and the TFT, an auxiliary capacitor Cs is disposed in parallel with the capacitor Clc.
FIG. 15A is a view illustrating a scanning timing chart of gate lines G1-G4 by means of the gate drivers in FIG. 14. FIG. 15B is a view illustrating pixel electrical potential waveforms of a pixel F (see FIG. 12) in green connected, for example, to the source line S3 and written first (pixel “G-first”), and of a pixel L (see FIG. 12) in red connected, for example, to the source line S2 and written later (“R-later”).
Hereinafter, the case of a liquid crystal display device in a normally white mode that reduces a transmission factor (becomes dark) as the voltage applied to the pixel becomes larger will be described. FIG. 15B shows the case in which the amplitude of the common voltage Vcom is set to 5.0V, the voltage to write the pixel F (G-first) (video signal Vsig) is set to 2.0V against the common voltage Vcom (intermediate tone), and the voltage to write the pixel L (R-later) (video signal Vsig) is set to 4.0V against the common voltage Vcom (black, dark). Since the influence of drawing voltage (field through voltage) ΔV generated when the TFT 102 is switched from on to off can be cancelled through adjustment of the common voltage Vcom (shift Vcom downward by ΔV), the influence is not illustrated at the waveform in FIG. 15B (the same applies to figures of other pixel electrical potential waveforms described later).
As shown in FIG. 15A, in each field, two gate lines are selected in one horizontal period, and the selected two gate lines are scanned in turn for every horizontal period. As depicted in FIG. 15B, the TFTs 102 connected to the selected gate lines turn on, and the video signals Vsigs applied from the source lines to the corresponding pixels 100 are written. Accordingly, the write timing of the pixel F (G-first) becomes WG in FIG. 15B and the write timing of pixel L (R-later) becomes WR. The pixel electrical potentials written at these timings WG and WR are maintained until those pixels are re-written in the next field.
FIG. 15B illustrates pixel electrical potential waveforms in an ideal state when the inter-pixel parasitic capacitance 104 is “0”. However, as mentioned above, the inconvenience of the occurrence of the capacitance 104 is generated at the point with no source line. FIG. 16A is a view illustrating the pixel electrical potential waveforms under the same voltage conditions as those of FIG. 15B by taking the capacitance 104 into consideration. FIG. 16B is a view illustrating the pixel electrical potential waveform in the case in which the amplitude of the common voltage Vcom is set to 5.0V, the write voltage of the pixel F (G-first) is set to 2.0V against the common voltage Vcom, and the write voltage of the pixel L (R-later) is set to 1.0V (white, bright), when the capacitance 104 is taken into account.
As shown in FIG. 16A and FIG. 16B, at the pixel F (G-first), the pixel electrical potential written by selecting the gate line G1 shifts to the direction going away from the common voltage Vcom (direction getting dark) by an electrical potential variation Vc in writing the pixel L (R-later) by selecting the gate line G2. The height of the variation Vc is expressed by the following equation (Eq.) (1):Vc=(Vsig(Fn-1)+Vsig(Fn))×Cpp/(Cs+Clc+Cpp)×α  (1)
In Eq. (1), “Vsig(Fn)” is the write voltage of the pixel L (R-later) in a current field, and “Vsig(Fn-1)” is the write voltage of the pixel L (R-later) in the preceding field. Therefore, in the case of FIG. 16A, “Vsig(Fn-1)+Vsig(Fn)=8.0V” is satisfied, and in the case of FIG. 16B, “Vsig(Fn-1)+Vsig(Fn)=2.0V” is satisfied. Cpp is a capacitance value of the parasitic capacitance 104, Cs is a capacitance value of the auxiliary capacitance Cs, Clc is a capacitance value of the liquid crystal capacitance Clc, and α is a proportional factor which value is determined in accordance with a panel structure, etc.
As described above, the larger the value of “Vsig(Fn-1)+Vsig(Fn)” is, the larger the value Vc of electrical potential variation becomes, and it does not depend on the magnitude of the amplitude of the common voltage Vcom.
The description above describes the case of the horizontal line inversion driving which differs in polarity of the common voltage Vcom among pixels adjacent to one another in the direction along the source line. That is, the description is the case in which, for instance, in FIG. 11, the horizontal line inversion driving differs in polarity of the common voltage Vcom among the pixels to be connected to the gate line G1 or G2 and the pixels to be connected to the gate line G3 or G4.
To perform the polarity inversion of the common electrode Vcom, a driving method referred to as dot inversion driving is known. In this driving method, the polarity of the common voltage Vcom differs between pixels adjacent to each other in the direction along the source line and between pixels adjacent to each other in the direction along the gate line. For example, in this driving method, the polarity of the common voltage Vcom differs between the pixel connected to gate line G2 and the pixel connected to gate line G3 and the pixel connected to gate line G1 and the pixel connected to gate line G3. In any case of the horizontal line inversion driving and the dot inversion driving, the polarities of the common voltages Vcoms at the respective pixels are inverted for each frame.
FIGS. 17A and 17B show the case of performing the dot inversion driving. Here, FIG. 17A illustrates the pixel electrical potential waveforms in the case in which the amplitude of the common voltage Vcom is set to 5.0V, the write voltage of the pixel F (G-first) is set to 2.0V (intermediate tone) against the common voltage Vcom, and the write voltage of the pixel L (R-later) is set to 4.0V (black) against the common voltage Vcom, taking the inter-pixel parasitic capacitance 104 into account. FIG. 17B illustrates the pixel electrical potential waveforms in the case in which the amplitude of the common voltage Vcom is set to 5.0V, the write voltage of the pixel F (G-first) is set to 2.0V against the common voltage Vcom, and the write voltage of the pixel L (R-later) is set to 1.0V (white) against the common voltage Vcom, taking the inter-pixel parasitic capacitance 104 into account.
As shown in FIGS. 17A and 17B, also when performing the dot inversion driving, in the same way as performing the horizontal line inversion driving, at the pixel F of G-first, in writing the pixel L of R-later by selecting the gate line G2, the pixel electrical potential, being written by selecting the gate line G1, shifts by the variation Vc.
Also in such a case, the larger the value of “Vsig(Fn-1)+Vsig(Fn)” is, the larger the value Vc of the electrical potential variation becomes, and the variation Vc does not depend on the amplitude of the common voltage Vcom as in the case of the horizontal line inversion driving.
In the horizontal line inversion driving, the potential variation occurs in such a manner as to increase the potential difference between the common voltage Vcom and the write voltage. In the dot inversion driving, in contrast, the potential variation occurs in such a manner as to decrease the potential difference between the common voltage Vcom and the write voltage.
In the normally white mode, wherein “white” is displayed when no voltage is applied and “black” is displayed when voltage is applied, the variations of Vc as given above result in making the pixel G-first darker than the actual display of the pixel in the case of the horizontal line inversion driving. In the case of the dot inversion driving, the variations described above result in making the pixel G-first brighter that the actual one. In contrast, since a normal voltage for the pixel electrical potential of the pixel G-later is written, displaying like a G raster results in displays of alternate bright and dark lines in a longitudinal direction also in both inversion driving.
Similar variations of the variation Vc also occur at the pixel R-first and at the pixel B-first.
The situation given above is not limited in the case of a strip arrangement of the pixels 100, and the same goes as the case of a delta arrangement.
The method disclosed by the foregoing Jpn. Pat. Appln. KOKAI Publication No. 2004-185006 cannot deal with the problem of display unevenness due to the electrical potential variations generated at the previously written pixels caused by such inter-pixel parasitic capacitance 104.